A phase-locked loop (PLL) is typically characterized by a certain, non-zero phase error (also referred to herein as phase offset or propagation delay (TPD)), which represents a phase difference between a reference clock input and a feedback clock input when the PLL is in a locked state. This phase difference, for example, may be caused by non-idealities and mismatches in circuit elements both within and outside of the PLL. The control of the phase error or phase difference is often one of the primary objectives in every PLL design (e.g., a phase difference less than a few hundred picoseconds may be desired).
A common approach for maintaining a low phase error is to design the PLL's charge pump so as to reduce its susceptibility to the various factors causing systematic and random mismatch in the output currents of the charge pump. For example, various circuit implementations exist that are known to improve the insensitivity of the charge pump currents to supply voltage variation, output voltage range, and device mismatch. However, these circuit implementations generally provide an optimal result for just a certain set of conditions (e.g., process, supply voltage, or output voltage/current) and charge pump architecture.
Another drawback to this approach is that these solutions generally do not provide active compensation for the current mismatch in the charge pump, which is translated into a charge difference in a loop filter of the PLL and consequently a timing difference or a phase error on the PLL input. Thus, these general approaches, for example, only offer an improvement that may be insufficient to meet the tight phase error specifications of current clock generator products. As a result, there is a need for improved PLL circuit techniques.